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rev. 3.1 2/2011 page 1 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm features ? 48 vdc to 12 vdc 25 a current multiplier - operating from standard 48 v or 24 v prm tm regulators ? high efficiency (>96%) reduces system power consumption ? high density (85 a/in 3 ) ? ?full chip? v ? i chip package enables surface mount, low impedance interconnect to system board ? contains built-in protection features: - overvoltage lockout - overcurrent - short circuit - overtemperature ? provides enable / disable control, internal temperature monitoring ? zvs / zcs resonant sine amplitude converter topology ? less than 50oc temperature rise at full load in typical applications typical applications ? high end computing systems ? automated test equipment ? high density power supplies ? communications systems description the v ? i chip tm current multiplier is a high efficiency (>96%) sine amplitude converter tm (sac tm ) operating from a 26 to 55 vdc primary bus to deliver an isolated output. the sine amplitude converter offers a low ac impedance beyond the bandwidth of most downstream regulators; therefore capacitance normally at the load can be located at the input to the sine amplitude converter. since the k factor of the vtm48ef120t025a00 is 1/4, the capacitance value can be reduced by a factor of 16, resulting in savings of board area, materials and total system cost. the vtm48ef120t025a00 is provided in a v ? i chip package compatible with standard pick-and-place and surface mount assembly processes. the co-molded v ? i chip package provides enhanced thermal management due to a large thermal interface area and superior thermal conductivity. the high conversion efficiency of the vtm48ef120t025a00 increases overall system efficiency and lowers operating costs compared to conventional approaches. the vtm48ef120t025a00 enables the utilization of factorized power architecture tm which provides efficiency and size benefits by lowering conversion and distribution losses and promoting high density point of load conversion. vtm tm current multiplier v in = 26 to 55 v v out = 6.5 to 13.8 v ( no load ) i out = 25 a ( nom ) k = 1/4 v in l o a d pr pc vc tm il os sg prm tm regulator cd -out +out -in +in pc vc tm -out +out -in +in regulator voltage transformer factorized power architecture tm vtm tm transformer (see application note an:024 ) c us ? s nrtl c us part number package style product grade f = j-lead t = -40 to 125c t = through hole m = -55 to 125c part numbering for storage and operating temperatures see section 6.0 general characteristics 120 x y 025a00 e 48 vtm typical application
rev. 3.1 2/2011 page 2 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm attribute symbol conditions / notes min typ max unit input voltage range v in no external vc applied 26 55 v dc vc applied 055 v in slew rate dv in /dt 1 v/s v in uv turn off v in _ uv module latched shutdown, 24 26 v no external vc applied, i out = 25a no load power dissipation p nl v in = 48 v 315 w v in = 26 v to 55 v 17 v in = 48 v, t c = 25oc 5.3 6.5 v in = 26 v to 55 v, t c = 25oc 9 inrush current peak i inrp vc enable, v in = 48 v, c out = 1000 f, 10 20 a r load = 471 m dc input current i in _ dc 7 a transfer ratio k k = v out /v in , i out = 0 a 1/4 v/v output voltage v out v out = v in ? k - i out ? r out , section 11 v output current (average) i out _ avg 25 a output current (peak) i out _ pk t peak < 10 ms, i out _ avg 25 a 37.5 a output power (average) p out _ avg i out _ avg 25 a 300 w v in = 48 v, i out = 25 a 95.0 96.0 efficiency (ambient) amb v in = 26 v to 55 v, i out = 25 a 93.5 % v in = 48 v, i out = 12.5 a 94.5 95.5 efficiency (hot) hot v in = 48 v, t c = 100c, i out = 25 a 94.5 95.6 % efficiency (over load range) 20% 5 a < i out < 25 a 80 % output resistance (cold) r out _ cold t c = -40c, i out = 25 a 4.9 6.7 9.0 m output resistance (ambient) r out _ amb t c = 25c, i out = 25 a 6.3 9.0 13.4 m output resistance (hot) r out _ hot t c = 100c, i out = 25 a 8.8 11.5 14.0 m switching frequency f sw 1.85 1.95 2.05 mhz output ripple frequency f sw _ rp 3.70 3.90 4.10 mhz output voltage ripple v out _ pp c out = 0 f, i out = 25 a, v in = 48 v, 150 285 mv 20 mhz bw, section 12 output inductance (parasitic) l out _ par frequency up to 30 mhz, 600 ph simulated j-lead model output capacitance (internal) c out _ int effective value at 12 v out 47 f output capacitance (external) c out _ ext vtm standalone operation. 1000 f v in pre-applied, vc enable protection overvoltage lockout v in _ ovlo + module latched shutdown 55.1 58.5 60 v overvoltage lockout t ovlo effective internal rc filter 8 s response time constant output overcurrent trip i ocp 26 39 55 a short circuit protection trip current i scp 26 a output overcurrent t ocp effective internal rc filter (integrative). 5.3 ms response time constant short circuit protection response time t scp from detection to cessation 1s of switching (instantaneous) thermal shutdown setpoint t j _ otp 125 130 135 oc reverse inrush curre nt protectio n reverse i nrush protection disabled for this product 1.0 absolute maximum voltage ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device. 2.0 electrical characteristics specifications apply over all line and load conditions unless otherwise noted; boldface specifications apply over the temperature range of -40c < t j < 125c (t-grade) ; all other specifications are at t j = 25oc unless otherwise noted. min max unit + in to - in . . . . . . . . . . . . . . . . . . . . . . . -1.0 60 v dc pc to - in . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 v dc tm to -in . . . . . . . . . . . . . . . . . . . . . . . . -0.3 7 v dc vc to - in . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 v dc min max unit + in / - in to + out / - out (hipot) ........ 2250 v dc + in / - in to + out / - out (working) ... 60 v dc + out to - out ....................................... -1.0 16 v dc
rev. 3.1 2/2011 page 3 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm signal type state attribute symbol conditions / notes min typ max unit external vc voltage v vc _ ext required for start up, and operation 11.5 16.5 v below 26 v. see section 7. vc = 11.5 v, v in = 0 v 115 150 vc current draw i vc vc = 11.5 v, v in > 26 v 0 ma vc = 16.5 v, v in > 26 v 0 steady fault mode. vc > 11.5 v 60 analog vc internal diode rating d vc _ int 100 v input vc internal resistor r vc - int 0.511 k vc internal resistor t vc _ coeff 900 ppm /c temperature coefficient start up vc start up pulse v vc _ sp tpeak <18 ms 20 v vc slew rate dvc/dt required for proper start up; 0.02 0.25 v/s vc inrush current i inr _ vc vc = 16.5 v, dvc/dt = 0.25 v/s 1 a vc to v out turn-on delay t on v in pre-applied, pc floating, 500 s vc enable, c pc = 0 f transitional vc to pc delay t vc_pc vc = 11.5 v to pc high, v in = 0 v, 75 125 s dvc/dt = 0.25 v/s internal vc capacitance c vc _ int vc = 0 v 3.2 f ? used to wake up powertrain circuit. ? a minimum of 11.5 v must be applied indefinitely for v in < 26 v to ensure normal operation. ? vc slew rate must be within range for a succesful start. ? prm vc can be used as valid wake-up signal source. ? internal resistance used in ?adaptive loop? compensation ? vc voltage may be continuously applied vtm control : vc 3.0 signal characteristics specifications apply over all line and load conditions unless otherwise noted; boldface specifications apply over the temperature range of -40c < t j < 125c (t-grade) ; all other specifications are at t j = 25c unless otherwise noted. signal type state attribute symbol conditions / notes min typ max unit pc voltage v pc 4.7 5 5.3 v analog steady pc source current i pc _ op 2ma output pc resistance (internal) r pc _ int internal pull down resistor 50 150 400 k start up pc source current i pc _ en 50 100 300 a pc capacitance (internal) c pc _ int section 7 1000 pf pc resistance (external) r pc _ s 60 k enable pc voltage v pc _ en 2 2.5 3 v digital disable pc voltage (disable) v pc _ dis 2 v input / ouput pc pull down current i pc _ pd 5.1 ma transitional pc disable time t pc _ dis _ t 5s pc fault response time t fr _ pc from fault to pc = 2 v 100 s ? the pc pin enables and disables the vtm. when held below 2 v, the vtm will be disabled. ? pc pin outputs 5 v during normal operation. pc pin is equal to 2.5 v during fault mode given v in > 26 v or vc > 11.5 v. ? after successful start up and under no fault condition, pc can be used as a 5 v regulated voltage source with a 2 ma maximum current. ? module will shutdown when pulled low with an impedance less than 400 ?. ? in an array of vtms, connect pc pin to synchronize start up. ? pc pin cannot sink current and will not disable other modules during fault mode. primary control : pc
rev. 3.1 2/2011 page 4 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm signal type state attribute symbol conditions / notes min typ max unit tm voltage v tm _ amb t j controller = 27c 2.95 3.00 3.05 v analog tm source current i tm 100 a output steady tm gain a tm 10 mv/c tm voltage ripple v tm _ pp c tm = 0 f, v in = 48 v, 120 200 mv i out = 25 a disable tm voltage v tm _ dis 0v digital output tm resistance (internal) r tm _ int internal pull down resistor 25 40 50 k transitional tm capacitance (external) c tm _ ext 50 pf (fault flag) tm fault response time t fr _ tm from fault to tm = 1.5 v 10 s ? the tm pin monitors the internal temperature of the vtm controller ic within an accuracy of 5c. ? can be used as a "power good" flag to verify that the vtm is operating. ? the tm pin has a room temperature setpoint of 3 v and approximate gain of 10 mv/c. ? output drives temperature shutdown comparator temperature monitor : tm 4.0 timing diagram 12 7 v in 1. initiated v c pulse 2. controller start 3. v in ramp up 4. v in = v ovlo 5. v in ramp down no v c pulse 6. overcurrent 7. start up on short circuit 8. pc driven low v out pc 3 v vc nl 5 v v ovlo tm v tm-amb c notes: C timing and voltage is not to scale C error pulse width is load dependent a: vc slew rate (dvc/dt) b: minimum vc pulse rate c: t ovlo d: t ocp e: output turn on delay (t on ) f: pc disable time (t pc_dis_t ) g: vc to pc delay (t vc_pc ) d i ssp i out i ocp v vc-ext 3 45 6 a b 8 g e f 26 v
rev. 3.1 2/2011 page 5 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm 5.0 application characteristics the following values, typical of an application environment, are collected at t c = 25oc unless otherwise noted. see associated figures for general trend data. attribute symbol conditions / notes typ unit no load power dissipation p nl v in = 48 v, pc enabled 5.1 w efficiency (ambient) amb v in = 48 v, i out = 25 a 96.0 % efficiency (hot) hot v in = 48 v, i out = 25 a, t c = 100oc 95.6 % output resistance (cold) r out _ cold v in = 48 v, i out = 25 a, t c = -40oc 7.4 m output resistance (ambient) r out _ amb v in = 48 v, i out = 25 a 9.4 m output resistance (hot) r out _ hot v in = 48 v, i out = 25 a, t c = 100oc 11.7 m output voltage ripple v out _ pp c out = 0 f, i out = 25 a, v in = 48 v, 198 mv 20 mhz bw, section 12 v out transient (positive) v out _ tran + i out _ step = 0 a to 25a, v in = 48 v, 650 mv i slew = 23 a /us v out transient (negative) v out _ tran - i out _ step = 25 a to 0 a, v in = 48 v 310 mv i slew = 91 a /us 1 3 5 7 9 11 26 29 32 35 38 41 43 46 49 52 55 no load power dissipation vs. line input voltage (v) no load power dissipation (w) -40? 25? 100? t : case 90 92 94 96 98 100 -40 -20 0 20 40 60 80 100 full load efficiency vs. case temperature case temperature (c) full load efficiency (%) 26 v 48 v 55 v v : in 0 5 10 15 20 25 30 35 40 45 50 60 64 68 72 76 80 84 88 92 96 100 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 p d efficiency & power dissipation -40c case load current (a) efficiency (%) 26 v 48 v 55 v v : in 26 v 48 v 55 v power dissipation (w) p d 0 4 8 12 16 20 24 28 32 68 72 76 80 84 88 92 96 100 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 efficiency & power dissipation 25c case load current (a) efficiency (%) 26 v 48 v 55 v v : in 26 v 48 v 55 v power dissipation (w) figure 1 ? no load power dissipation vs. v in figure 2 ? full load efficiency vs. temperature figure 3 ? efficiency and power dissipation at ?40c figure 4 ? efficiency and power dissipation at 25c
rev. 3.1 2/2011 page 6 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm figure 10 ? start up from application of v in ; vc pre-applied c out = 1000 f 0 5 10 15 20 25 30 35 40 45 0 2 4 6 8 10 12 14 16 safe operating area output voltage (v) output current (a) 10 ms max continuous figure 8 ? safe operating area figure 9 ? full load ripple, 100 f c in ; no external c out . board mounted module, scope setting : 20 mhz analog bw 50 75 100 125 150 175 200 225 250 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 load current (a) ripple (mv pk-pk) 26 v 48 v 55 v v : in output voltage ripple vs. load figure 7 ? v ripple vs. i out ; no external c out . board mounted module, scope setting : 20 mhz analog bw p d 0 4 8 12 16 20 24 28 32 68 72 76 80 84 88 92 96 100 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 efficiency & power dissipation 100c case load current (a) efficiency (%) 26 v 48 v 55 v v : in 26 v 48 v 55 v power dissipation (w) 4 6 8 10 12 14 -40 -20 0 20 40 60 80 100 r out vs. t case at v in = 48 v case temperature (c) rout (m ) i : out 12.5 a 25 a figure 5 ? efficiency and power dissipation at 100c figure 6 ? r out vs. temperature
rev. 3.1 2/2011 page 7 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm figure 13 ? 25 a ? 0 a transient response: c in = 100 f, no external c out figure 12 ? 0 a? 25 a transient response: c in = 100 f, no external c out figure 11 ? start up from application of vc; v in pre-applied c out = 1000 f
rev. 3.1 2/2011 page 8 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm attribute symbol conditions / notes min typ max unit mechanical length l 32.25 / [1.270] 32.5 / [1.280] 32.75 / [1.289] mm/[in] width w 21.75 / [0.856] 22.0 / [0.866] 22.25 / [0.876] mm/[in] height h 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm/[in] volume vol no heat sink 4.81 / [0.294] cm 3 /[in 3 ] weight w 15.0 / [0.53] g/[oz] nickel 0.51 2.03 lead finish palladium 0.02 0.15 m gold 0.003 0.051 thermal vtm48ef120t025a00 (t-grade) -40 125 c operating temperature t j vtm48ef120m025a00 (m-grade) -55 125 c vtm48et120t025a00 (t-grade) -40 125 c vtm48et120m025a00 (m-grade) -55 125 c thermal resistance jc isothermal heat sink and 1 c/w isothermal internal pcb thermal capacity 5 ws/c assembly peak compressive force supported by j-lead only 6lbs applied to case (z-axis) 5.41 lbs / in 2 vtm48ef120t025a00 (t-grade) -40 125 c storage temperature t st vtm48ef120m025a00 (m-grade) -65 125 c vtm48et120t025a00 (t-grade) -40 125 c vtm48et120m025a00 ( m-grade) -65 125 c moisture sensitivity level msl msl 6, tob = 4 hrs msl 5 esd hbm 1000 esd withstand esd cdm 400 v dc soldering peak temperature during reflow msl 6, tob = 4 hrs 245 c msl 5 225 c peak time above 245c 60 90 s peak heating rate during reflow 1.5 3 c/s peak cooling rate post reflow 1.5 6 c/s safety working voltage (in ? out) v in _ out 60 v dc isolation voltage (hipot) v hipot 2250 v dc isolation capacitance c in _ out unpowered unit 2500 3200 3800 pf isolation resistance r in _ out 10 m mtbf mil-hdbk-217 plus parts count; 1.83 mhrs 25oc ground benign, stationary, indoors / computer profile telcordia issue 2 - method i case 1; 7.3 mhrs ground benign, controlled ctuvus agency approvals / standards curus ce mark rohs 6 of 6 human body model, "jedec jesd 22-a114-f" charge device model, "jedec jesd 22-c101-d" 6.0 general characteristics specifications apply over all line and load conditions unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t j < 125oc (t-grade) ; all other specifications are at t j = 25c unless otherwise noted.
rev. 3.1 2/2011 page 9 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm 7.0 using the control signals vc, pc, tm, im the vtm control (vc) pin is an input pin which powers the internal vcc circuitry when within the specified voltage range of 11.5 v to 16.5 v. this voltage is required for vtm tm current multiplier start up and must be applied as long as the input is below 26 v. in order to ensure a proper start, the slew rate of the applied voltage must be within the specified range. some additional notes on the using the vc pin: ? in most applications, the vtm module will be powered by an upstream prm tm regulator which provides a 10 ms vc pulse during start up. in these applications the vc pins of the prm regulator and vtm current multiplier should be tied together. ? the vc voltage can be applied indefinitely allowing for continuous operation down to 0 v in . ? the fault response of the vtm module is latching. a positive edge on vc is required in order to restart the unit. if vc is continuously applied the pc pin may be toggled to restart the vtm module. primary control (pc) pin can be used to accomplish the following functions: ? delayed start: upon the application of vc, the pc pin will source a constant 100 a current to the internal rc network. adding an external capacitor will allow further delay in reaching the 2.5 v threshold for module start. ? auxiliary voltage source: once enabled in regular operational conditions (no fault), each vtm pc provides a regulated 5 v, 2 ma voltage source. ? output disable: pc pin can be actively pulled down in order to disable the module. pull down impedance shall be lower than 400 . ? fault detection flag: the pc 5 v voltage source is internally turned off as soon as a fault is detected. it is important to notice that pc doesn?t have current sink capability. therefore, in an array, pc line will not be capable of disabling neighboring modules if a fault is detected. ? fault reset: pc may be toggled to restart the unit if vc is continuously applied. temperature monitor (tm) pin provides a voltage proportional to the absolute temperature of the converter control ic. it can be used to accomplish the following functions: ? monitor the control ic temperature: the temperature in kelvin is equal to the voltage on the tm pin scaled by 100. (i.e. 3.0 v = 300 k = 27oc). if a heat sink is applied, tm can be used to thermally protect the system. ? fault detection flag: the tm voltage source is internally turned off as soon as a fault is detected. for system monitoring purposes (microcontroller interface) faults are detected on falling edges of tm signal. 8.0 start up behavior depending on the sequencing of the vc with respect to the input voltage, the behavior during start up will vary as follows: ? normal operation (vc applied prior to v in ): in this case the controller is active prior to ramping the input. when the input voltage is applied, the vtm output voltage will track the input (see figure 10). the inrush current is determined by the input voltage rate of rise and output capacitance. if the vc voltage is removed prior to the input reaching 26 v, the vtm may shut down. ? stand-alone operation (vc applied after v in ): in this case the vtm output will begin to rise upon the application of the vc voltage (see figure 11). the adaptive soft start circuit (see section 11) may vary the ouput rate of rise in order to limit the inrush current to its maximum level. when starting into high capacitance, or a short, the output current will be limited for a maximum of 120 /sec. after this period, the adaptive soft start circuit will time out and the vtm module may shut down. no restart will be attempted until vc is re-applied or pc is toggled. the maximum output capacitance is limited to 1000 f in this mode of operation to ensure a sucessful start. 9.0 thermal considerations v ? i chip tm products are multi-chip modules whose temperature distribution varies greatly for each part number as well as with the input / output conditions, thermal management and environmental conditions. maintaining the top of the vtm48ef120t025a00 case to less than 100oc will keep all junctions within the v ? i chip module below 125oc for most applications. the percent of total heat dissipated through the top surface versus through the j-lead is entirely dependent on the particular mechanical and thermal environment. the heat dissipated through the top surface is typically 60%. the heat dissipated through the j-lead onto the pcb board surface is typically 40%. use 100% top surface dissipation when designing for a conservative cooling solution. it is not recommended to use a v ? i chip module for an extended period of time at full load without proper heat sinking.
rev. 3.1 2/2011 page 10 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm -v out +v in v ref tm pc temperature dependent voltage source -v in 2.5 v 100 a 5 v 40 k 1000 pf 10.5 v 2.5 v differential primary current sensing v ref enable 1.5 k synchronous rectification primary stage & resonant tank pc pull-up & source overtemperature protection fast current limit vc c in 18 v power transformer q1 q2 q6 primary gate drive secondary gate drive fault logic regulator supply enable adaptive soft start enable q5 cr lr 0.01 f 1 k 2 ma c out modulator enable 150 k v dd v dd v dd +v out q3 q4 gate drive supply d vc_int r vc_int v in ovlo uvlo slow current limit over current protection 10.0 vtm48ef120t025a00 block diagram
rev. 3.1 2/2011 page 11 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm 11.0 sine amplitude converter tm point of load conversion the sine amplitude converter (sac tm ) uses a high frequency resonant tank to move energy from input to output. (the resonant tank is formed by cr and leakage inductance lr in the power transformer windings as shown in the vtm tm module block diagram. see section 10). the resonant lc tank, operated at high frequency, is amplitude modulated as a function of input voltage and output current. a small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionality and is key to achieving power density. the vtm48ef120t025a00 sac can be simplified into the following model: at no load: v out = v in ? k (1) k represents the ?turns ratio? of the sac. rearranging eq (1): k= v out (2) v in in the presence of load, v out is represented by: v out = v in ? k ? i out ? r out (3) and i out is represented by: i out = i in ?i q (4) k r out represents the impedance of the sac, and is a function of the r dson of the input and output mosfets and the winding resistance of the power transformer. i q represents the quiescent current of the sac control and gate drive circuitry. the use of dc voltage transformation provides additional interesting attributes. assuming that r out = 0 and i q = 0 a, eq. (3) now becomes eq. (1) and is essentially load independent, resistor r is now placed in series with v in as shown in figure 15. the relationship between v in and v out becomes: v out = (v in ?i in ? r) ? k (5) substituting the simplified version of eq. (4) (i q is assumed = 0 a) into eq. (5) yields: v out = v in ? k ? i out ? r ? k 2 (6) l in = 5 nh + + v out c out v in v i k + + c in i out r c out i q r out r c in 109 ma 1/4 ? i out 1/4 ? v in 9.0 m r cin 0.57 m 973 ph 3.13 r cout 430 47 f l out = 600 ph 2f i q l in = 5.7 nh i out r out v in v out r sac k = 1/32 vin vout + ? v in v out r sac tm k = 1/32 figure 15 ? k = 1/32 sine amplitude converter with series input resistor figure 14 ? v ? i chip tm ac model c out c in
rev. 3.1 2/2011 page 12 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm this is similar in form to eq. (3), where r out is used to represent the characteristic impedance of the sac tm . however, in this case a real r on the input side of the sac is effectively scaled by k 2 with respect to the output. assuming that r = 1 , the effective r as seen from the secondary side is 0.98 m , with k = 1/32 as shown in figure 15. a similar exercise should be performed with the additon of a capacitor or shunt impedance at the input to the sac. a switch in series with v in is added to the circuit. this is depicted in figure 16. a change in v in with the switch closed would result in a change in capacitor current according to the following equation: i c (t) = c dv in (7) dt assume that with the capacitor charged to v in , the switch is opened and the capacitor is discharged through the idealized sac. in this case, i c =i out ? k (8) substituting eq. (1) and (8) into eq. (7) reveals: i out = c ? dv out (9) k 2 dt the equation in terms of the output has yielded a k 2 scaling factor for c, specified in the denominator of the equation. a k factor less than unity, results in an effectively larger capacitance on the output when expressed in terms of the input. with a k= 1/32 as shown in figure 16, c = 1 f would appear as c = 1024 f when viewed from the output. low impedance is a key requirement for powering a high- current, low voltage load efficiently. a switching regulation stage should have minimal impedance while simultaneously providing appropriate filtering for any switched current. the use of a sac between the regulation stage and the point of load provides a dual benefit of scaling down series impedance leading back to the source and scaling up shunt capacitance or energy storage as a function of its k factor squared. however, the benefits are not useful if the series impedance of the sac is too high. the impedance of the sac must be low, i.e. well beyond the crossover frequency of the system. a solution for keeping the impedance of the sac low involves switching at a high frequency. this enables small magnetic components because magnetizing currents remain low. small magnetics mean small path lengths for turns. use of low loss core material at high frequencies also reduces core losses. the two main terms of power loss in the vtm tm module are: - no load power dissipation (p nl ): defined as the power used to power up the module with an enabled powertrain at no load. - resistive loss (r out ): refers to the power loss across the vtm modeled as pure resistive impedance. p dissipated = p nl + p r out (10) therefore, p out = p in ?p dissipated = p in ?p nl ?p r out (11) the above relations can be combined to calculate the overall module efficiency: = p out = p in ?p nl ?p r out (12) p in p in = v in ? i in ?p nl ?(i out ) 2 ? r out v in ? i in =1 ? ( p nl + (i out ) 2 ? r out ) v in ? i in c s sac k = 1/32 vin vout + ? v in v out c sac tm k = 1/32 figure 16 ? sine amplitude converter tm with input capacitor s
rev. 3.1 2/2011 page 13 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm 12.0 input and output filter design a major advantage of a sac tm system versus a conventional pwm converter is that the former does not require large functional filters. the resonant lc tank, operated at extreme high frequency, is amplitude modulated as a function of input voltage and output current and efficiently transfers charge through the isolation transformer. a small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionality and is key to achieving high power density. this paradigm shift requires system design to carefully evaluate external filters in order to: 1.guarantee low source impedance. to take full advantage of the vtm tm module dynamic response, the impedance presented to its input terminals must be low from dc to approximately 5 mhz. input capacitance may be added to improve transient performance or compensate for high source impedance. 2.further reduce input and/or output voltage ripple without sacrificing dynamic response. given the wide bandwidth of the vtm module, the source response is generally the limiting factor in the overall system response. anomalies in the response of the source will appear at the output of the vtm module multiplied by its k factor. 3.protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures. the v ? i chip tm module input/output voltage ranges must not be exceeded. an internal overvoltage lockout function prevents operation outside of the normal operating input range. even during this condition, the powertrain is exposed to the applied voltage and power mosfets must withstand it. 13.0 capacitive filtering considerations for a sine amplitude converter tm it is important to consider the impact of adding input and output capacitance to a sine amplitude converter on the system as a whole. both the capacitance value and the effective impedance of the capacitor must be considered. a sine amplitude converter has a dc r out value which has already been discussed in section 11. the ac r out of the sac contains several terms: ? resonant tank impedance ? input lead inductance and internal capacitance ? output lead inductance and internal capacitance the values of these terms are shown in the behavioral model in section 11. it is important to note on which side of the transformer these impedances appear and how they reflect across the transformer given the k factor. the overall ac impedance varies from model to model. for most models it is dominated by dc r out value from dc to beyond 500 khz. the behavioral model in section 11 should be used to approximate the ac impedance of the specific model. any capacitors placed at the output of the vtm module reflect back to the input of the module by the square of the k factor (eq. 9) with the impedance of the module appearing in series. it is very important to keep this in mind when using a prm tm regulator to power the vtm module. most prm modules have a limit on the maximum amount of capacitance that can be applied to the output. this capacitance includes both the prm output capacitance and the vtm output capacitance reflected back to the input. in prm remote sense applications, it is important to consider the reflected value of vtm output capacitance when designing and compensating the prm control loop. capacitance placed at the input of the vtm module appear to the load reflected by the k factor with the impedance of the vtm module in series. in step-down ratios, the effective capacitance is increased by the k factor. the effective esr of the capacitor is decreased by the square of the k factor, but the impedance of the module appears in series. still, in most step-down vtm modules an electrolytic capacitor placed at the input of the module will have a lower effective impedance compared to an electrolytic capacitor placed at the output. this is important to consider when placing capacitors at the output of the module. even though the capacitor may be placed at the output, the majority of the ac current will be sourced from the lower impedance, which in most cases will be the module. this should be studied carefully in any system design using a module. in most cases, it should be clear that electrolytic output capacitors are not necessary to design a stable, well-bypassed system.
rev. 3.1 2/2011 page 14 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm v in v out + C dc z in_eq1 z in_eq2 z out_eq1 z out_eq2 load vtm1 r o_1 vtm2 r o_2 vtmn r o_n z out_eqn z in_eqn figure 17 ? vtm tm current multiplier array 14.0 current sharing the sac tm topology bases its performance on efficient transfer of energy through a transformer without the need of closed loop control. for this reason, the transfer characteristic can be approximated by an ideal transformer with some resistive drop and positive temperature coefficient. this type of characteristic is close to the impedance characteristic of a dc power distribution system, both in behavior (ac dynamic) and absolute value (dc dynamic). when connected in an array with the same k factor, the vtm module will inherently share the load current (typically 5%) with parallel units according to the equivalent impedance divider that the system implements from the power source to the point of load. some general recommendations to achieve matched array impedances: ? dedicate common copper planes within the pcb to deliver and return the current to the modules. ? provide the pcb layout as symmetric as possible. ? apply same input / output filters (if present) to each unit. for further details see an:016 using bcm? bus converters in high power arrays . 15.0 fuse selection in order to provide flexibility in configuring power systems v ? i chip tm products are not internally fused. input line fusing of v ? i chip products is recommended at system level to provide thermal protection in case of catastrophic failure. the fuse shall be selected by closely matching system requirements with the following characteristics: ? current rating (usually greater than maximum current of vtm module) ? maximum voltage rating (usually greater than the maximum possible input voltage) ? ambient temperature ? nominal melting i 2 t 16.0 reverse operation the vtm48ef120t025a00 is capable of reverse operation. if a voltage is present at the output which satisfies the condition v out > v in ? k at the time the vc voltage is applied, or after the unit has started, then energy will be transferred from secondary to primary. the input to output ratio will be maintained. the vtm48ef120t025a00 will continue to operate in reverse as long as the input and output are within the specified limits. the vtm48ef120t025a00 has not been qualified for continuous operation (>10 ms) in the reverse direction.
rev. 3.1 2/2011 page 15 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm inch mm notes: . dimensions are . 2. unless otherwise specified, tolerances are: .x / [.xx] = +/-0.25 / [.01]; .xx / [.xxx] = +/-0.13 / [.005] 3. p roduct marking on top surface dxf and pdf files are available on vicorpower.com 4 inch mm . dimensions are . 2. unless otherwise specified, tolerances are: .x / [.xx] = +/-0.25 / [.01]; .xx / [.xxx] = +/-0.13 / [.005] 3. p roduct marking on top surface dxf and pdf files are available on vicorpower.com 4 17.2 j-lead package recommended land pattern mm (inch) 17.1 j-lead package mechanical drawing click here to view original mechanical drawings on the vicor website.
rev. 3.1 2/2011 page 16 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm inch mm notes: . dimensions are . 2. unless otherwise specified, tolerances are: .x / [.xx] = +/-0.25 / [.01]; .xx / [.xxx] = +/-0.13 / [.005] 3. p roduct marking on top surface dxf and pdf files are available on vicorpower.com 4 inch mm . dimensions are . 2. unless otherwise specified, tolerances are: .x / [.xx] = +/-0.25 / [.01]; .xx / [.xxx] = +/-0.13 / [.005] 3. p roduct marking on top surface dxf and pdf files are available on vicorpower.com 4 17.4 through hole package recommended land pattern mm (inch) 17.3 through hole package mechanical drawing click here to view original mechanical drawings on the vicor website.
rev. 3.1 2/2011 page 17 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm notes: 1. maintain 3.50 (0.138) dia. keep-out zone free of copper, all pcb layers. 2. (a) minimum recommended pitch is 39.50 (1.555) this provides 7.00 (0.275) component edge-to-edge spacing, and 0.50 (0.020) clearance between vicor heat sinks. (b) minimum recommended pitch is 41.00 (1.614). this provides 8.50 (0.334) component edge-to-edge spacing, and 2.00 (0.079) clearance between vicor heat sinks. 3. v? chip tm module land pattern shown for reference only, actual land pattern may differ. dimensions from edges of land pattern to push?in holes will be the same for all full size v? chip products. 4. rohs compliant per cst?001 latest revision. (no grounding clips) (with grounding clips) 5. unless otherwise specified: dimensions are mm (inches) tolerances are: x.x (x.xx) = ?.3 (0.01) x.xx (x.xxx) = ?.13 (0.005) 6. plated through holes for grounding clips (33855) shown for reference, heat sink orientation and device pitch will dictate final grounding solution. 17.5 recommended heat sink push pin location -in pc vc tm +in -out +out -out +out bottom view a b c d e f g h j k l m n p r t 4 3 2 1 a b c d e h j k l m n p r t 17.6 vtm tm module pin configuration signal name pin designation +in a1-e1, a2-e2 ?in l1-t1, l2-t2 tm h1, h2 vc j1, j2 pc k1, k2 +out a3-d3, a4-d4, j3-m3, j4-m4 ?out e3-h3, e4-h4, n3-t3, n4-t4 click here to view original mechanical drawings on the vicor website.
rev. 3.1 2/2011 page 18 of 18 v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vicorpower.com x 120 025a00 y e 48 vtm vicor?s comprehensive line of power solutions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. all sales are subject to vicor?s terms and conditions of sale, which are available upon request. specifications are subject to change without notice. intellectual property notice vicor and its subsidiaries own intellectual property (including issued u.s. and foreign patents and pending patent applications) relating to the products described in this data sheet. interested parties should contact vicor's intellectual property department. the products described on this data sheet are protected by the following u.s. patents numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; d496,906; d505,114; d506,438; d509,472; and for use under 6,975,098 and 6,984,965. vicor corporation 25 frontage road andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email customer service: custserv@vicorpower.com technical support: apps@vicorpower.com warranty vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. this warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. vicor shall not be liable for collateral or consequential damage. this warranty is extended to the original purchaser only. except for the foregoing express warranty, vicor makes no warranty, express or implied, including, but not limited to, the warranty of merchantability or fitness for a particular purpose. vicor will repair or replace defective products in accordance with its own best judgement. for service under this warranty, the buyer must contact vicor to obtain a return material authorization (rma) number and shipping instructions. products returned without prior authorization will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all reshipment charges if the product was defective within the terms of this warranty. information published by vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. per vicor terms and conditions of sale, the user of vicor components in life support applications assumes all risks of such use and indemnifies vicor against all damages.

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